1. Field of the Invention
The present invention relates to a process for preparing a complementary MOS integrated circuit, more particularly, it relates to a short channel type complementary MOS integrated circuit which has a short channel length.
2. Description of Prior Art
Referring to FIGS. 1 and 2, the conventional process for preparing a silicon gate complementary MOS integrated circuit will be illustrated.
For example, a P-well (2) (1 .times. 10.sup.16 atoms/cm.sup.3) is formed at a part of a N-type silicon substrate (1) having a concentration of an impurity of 4 .times. 10.sup.14 atoms, by an ion injection method.
Then, a field oxide membrane 3 is formed on a region of a MOS transistor except the source-drain-gate of the MOS transistor. If necessary, a field dope is applied in this case. Then, a gate oxide membrane 4 having a thickness of about 1000 A 4 and a polycrystalline silicon having a thickness of about 4000 A 5 are respectively formed for a width of less than 5 microns. By the photo-engraving method, the predetermined parts such as a gate region are left. The structure in the stage is shown in FIG. 1.
An oxide membrane (not shown) is formed on the entire surface and then, the oxide membrane at the region for applying the P-channel source-drain diffusion, is removed by the photo-engraving method A P-type impurity such as boron is diffused into it by the conventional thermal diffusing method whereby the source 6 and the drain 7 (the concentration of the impurity at the surface of 10.sup.20 atoms/cm.sup.3) of the P-channel MOS transistor are formed.
Then, the oxide membrane (not shown) is formed on the entire surface and then, the oxide membrane at the region for applying the N-channel source-drain diffusion is removed by the photo-engraving method. A N-type impurity such as arsenic and phosphorus, is diffused into it by the conventional thermal diffusing method whereby the source 8 and the drain 9 the concentration of the impurity at the surface of 10.sup.21 atoms/cm.sup.3) of the N-channel MOS transistor are formed.
Then, the oxide membrane 10 is formed on the entire surface and a contact hole is formed for an aluminum wiring 11.
The structure in the stage is shown in FIG. 2. The diffusion depth at the source regions 6, 8 and the drain regions 7, 9 are about 1.5 microns. In the method, the source drain regions 6, 7 and 8, 9 are formed by diffusing the impurities with the mask of the gate polycrystalline silicon 5, whereby a self-matching gate structure is given.
For example, the structure of the N-channel MOS transistor near the gate polycrystalline silicon 5 is shown in FIG. 3. The source-drain regions 8, 9 are spread below the gate 5 for the diffusion depth to lateral direction. Accordingly, the effective channel length L.sub.eff is L-2Xj wherein L designates a width of the gate polycrystalline silicon 5 and Xj designates a diffusion depth. In order to obtain a high density structure of the complementary MOS integrated circuit, L should be minimized. However, when Xj is high, the control of L.sub.eff is difficult whereby the source-drain withstand voltage is decreased. On the contrary, when Xj is too low, the formation of the electrode in the source-drain region is difficult.
Accordingly, it has been difficult to decrease L to less than 5 microns in the structure of FIG. 3 as far as the conventional electrode forming method is employed.
In order to overcome the disadvantages, the other process having the steps of FIGS. 4 to 8 has been known.
In the process, in accordance with the former process having the step of FIG. 1, the P-well 2 and the field oxide membrane are formed as shown in FIG. 4.
Then, an oxide membrane (not shown) is formed on the entire surface and a hole is formed in the P-channel source-drain region, and the P-type impurity such as boron is diffused from it by the conventional thermal diffusion method whereby the source 6 and the drain 7 are formed.
Then, an oxide membrane (not shown) is formed on the entire surface and a hole is formed in the N channel source-drain region and the N-type impurity such as phosphorus is diffused into it by the conventional thermal diffusion whereby the source 8 and the drain 9 are formed. Then, the oxide membrane in the active region of the transistor is removed and a gate oxide membrane 4 is formed in the active region. The structure in the stage is shown in FIG. 5.
Then, a polycrystalline silicon membrane is formed, and the gate polycrystalline silicon 5 is left in the region between the source-drain as shown in FIG. 6 by the photo-engraving method. If necessary, the impurity is diffused into the polycrystalline silicon.
Then, the P-type impurity such as boron is injected in only the P-channel source-drain-gate region and the N-type impurity such as phosphorus is injected by the conventional ion injection in only the N-channel source-drain-gate region while masking the other part with the photoresist membrane.
The second source 12 and drain 13 are formed by the ion injection. The structure in the stage is shown in FIG. 7.
Then, the oxide membrane 10 is formed on the entire surface, and a contact hole is formed for the aluminum wiring 11. The structure in the stage is shown in FIG. 8.
The contact holes are formed at the first source-drain regions 6, 7 and 8, 9.
In accordance with the latter process, as shown in FIG. 8, the source-drain is not diffused below the gate polycrystalline silicon 5 as shown in FIG. 3 even though the diffusion depth of the first source-drains 6, 7 and 8, 9 are relatively deep. Moreover, it is unnecessary to form an electrode for the second source-drain 12, 13 whereby the depth of the second source-drain can be thin. Accordingly, the diffusion of the second source-drain 12, 13 below the gate polycrystalline silicon 5 can be effectively prevented and the width of the gate polycrystalline silicon L can be decreased.
However, in the latter process, the contact holes for the electrodes and the first source-drains 6, 7 and 8, 9 are separately formed. Accordingly, the steps are increased and an allowance for masking for the contact holes should be given in high level and the process has not been satisfactory for the preparation of the circuit having high density.